3rd ANNUAL FUNDAMENTALS CLASS
"SOI Devices and Circuits"
-
Fundamentals of SOI MOSFETs: Scaling
and Performance
Yuan Taur, University
of California,
San Diego
-
Circuit Design with SOI
Andrew Marshall,
Texas Instruments Inc.
The SOI fundamental class
is dedicated to attendees who want to get a basic knowledge of SOI
MOSFET device physics and circuits design. Two lectures of 1.5 hours
each will be given by world recognized experts in their respective
fields, Professor Yuan Taur (University
of California,
San Diego) and Dr. Andrew Marshall (Texas
Instruments).
Professor Taur will cover the device fundamentals of SOI MOSFETs.
For any given technology node, CMOS performance is limited by
the shortest channel length that can be made while maintaining
robust 2-D electrostatic integrity.
The scale length theories for both partially depleted and
fully-depleted SOI MOSFETs will be discussed in detail, leading to
the guideline of minimum channel length as a function of the film
thickness, with an emphasis on the important role of the backgate in
scaling. A two-region
scale length model that takes both the vertical and the lateral
fields into account is needed to deal with relatively thick, high-k
gate dielectrics. The
course will give useful guidelines that, with quantum mechanical
considerations, allow the projection of scaling limits for bulk,
SOI, double-gate, and nanowire MOSFETs.
Dr. Marshall will
speak on Circuit Design with SOI. In
some ways, circuit design in silicon-on-insulator processes varies
significantly from that of conventional bulk silicon. In other
aspects it can be very similar. This class will discuss the
similarities and different aspects of circuit design for partially
and fully depleted silicon on insulator technologies with planar and
FinFET device types.
Following a brief overview of SOI Components and Device
Properties, a comparison of SOI and Bulk advantages and
disadvantages will be described as a way of selecting a process for
a particular application. Discussion at this point covers MOS
devices, Bipolar Transistors, Diodes and Passive Components. Logic,
Memory and Analog Circuit Design in SOI are discussed, together with
discussion of low power design and reliability issues.
FUNDAMENTALS CLASS CHAIR
Samuel Fung
TSMC
khfung@tsmc.com
2009 IEEE INTERNATIONAL SOI CONFERENCE