2009 IEEE INTERNATIONAL SOI CONFERENCE35th ANNUAL SHORT COURSE
"Ultra-thin SOI Devices: The Way to the Future"
32nm CMOS processes are ramping up and 22nm are under development. A conventional bulk CMOS scheme is still pursued but due to the physical limitations inherent to device scaling there is now a strong interest in alternative solutions that would enable to maintain the performance without increasing the leakage. The main difficulty is to control the short channel effects and most of the candidates to achieve this are ultra-thin SOI devices either as 2D or 3D structures: multi-gate (MG), FinFET and more fancy names. All these devices have a common point: they are operating in a fully-depleted mode. Five renowned instructors will give an overview of these different devices dealing with related topics such as process, process integration, electrical operation, device physics, modeling and circuit design including memories. The instructors have been selected to bring their different views on these new devices so that the audience may understand that there are several possible candidates that could lead to a potential interesting competition.
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Multiple Gate Devices and Technology
Thomas Ernst, LETI -
Process & Device Technologies for FinFET and Its Alternative Devices
Atsushi Yagishita, -
FinFETs: The Answer to the End of Scaling?
Andres Bryant, IBM -
Multi-Gate MOSFET Physics and Design Insights
Jerry Fossum, -
Olivier Thomas, CEA-LETI
SHORT COURSE CHAIR
Jean-Luc Pelloie
ARM
jean-luc.pelloie@arm.comroduct
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